Rapid development of consumer electronics imposes an increasingly high demand and performance requirement on an integrated voltage regulator (IVR) in a power management integrated circuit (PMIC) in the electronics, and also requires a higher output loading capability of an IVR. A main trend is to improve the loading capability by using a multiphase parallel DCDC circuit. In addition, a response of the IVR to a transient jump of an output load is required to be as fast as possible, and a common method is increasing a switching frequency of the IVR or increasing a loop bandwidth.
In a scenario in which an output loading capability of an IVR is required to reach tens of amperes to hundreds of amperes, a quantity of parallel DCDC circuits needs to reach 16 phases, 32 phases, or more phases. As shown in FIG. 1, a block diagram of a principle of a 4-phase parallel buck conversion (BUCK) type DCDC circuit is provided. An output voltage (VEAOUT) of an error amplifier (EA) is connected to negative ends of four comparators (COMPs), positive ends of the COMPs are separately connected to a preset triangular wave signal (VSAW) such that square voltage signals having a predetermined duty cycle are separately generated, and an output signal V0 is obtained by using a power stage circuit including a buffer (BUF), two triodes, output inductors L1, L2, L3, and L4, and an output capacitor C0. A 16-phase parallel BUCK is used as an example. Similar to the 4-phase parallel BUCK, the 16-phase parallel BUCK also shares an output of an EA.
During actual layout of a circuit floor plan (floorplan), in one solution, a layout position of an EA is disposed at a center position of a die, and to reduce a delay to a power stage circuit, COMPs are disposed as close as possible to the power stage circuit. As shown in FIG. 2, a layout floor plan in which a 16-phase parallel DCDC circuit is extended by using an EA is provided. In FIG. 2, every two 1-phase power stage circuits form a group, each 1-phase power stage circuit is connected to a COMP, and the COMP is close to the corresponding power stage circuit. In another solution shown in FIG. 3, a layout position of an EA is disposed at a center position of a die, 16 COMPs are separately disposed around the EA, and each of the COMPs is connected to a corresponding 1-phase power stage circuit through a long trace.
In the solution in FIG. 2, if a die has a size of 4 mm*4 mm, it means a trace of VEAOUT needs to be at least 8 millimeters (mm). For an output of the EA, a longer trace layout indicates a larger parasitic capacitance and a larger parasitic resistance thereon, causing a lower frequency of a parasitic pole. Therefore, a high loop bandwidth design is greatly affected, and consequently a loop transient response is deteriorated. Particularly, when a quantity of parallel phases becomes larger, an area of a die becomes larger, and both a trace length and parasitics of the EA are increased. In a solution in FIG. 3, if a die has a size of 4 mm*4 mm, it means an output trace of each COMP needs to be at least 2 mm. For an output of the COMP, a longer trace layout indicates a larger parasitic capacitance and a larger parasitic resistance thereon, causing a lower frequency of a parasitic pole. Therefore, a loop delay is greatly affected, resulting in an increase in an overshoot or an undershoot during a transient response, and consequently the loop transient response is deteriorated.